Featured topics
Upcoming posts will focus on practical engineering workflows rather than generic AI coding advice.
- AI Verilog generation
- RTL debug with simulator logs
- CBB/IP reuse patterns
Blog
AI RTL generation notes
Public writing on RTL generation, simulation-driven repair, assertion-aware verification, and reusable CBB/IP workflows.
Documentation first
For current product guidance, use the public docs and use-case pages linked from this site.