Community

genRTL community

Discuss AI RTL generation, Verilog/SystemVerilog workflows, simulation debug, and CBB/IP reuse with other hardware engineers.

Discussion topics

The public community focuses on product feedback, workflow examples, CBB/IP suggestions, and practical RTL design questions.

  • AI RTL generation
  • Simulator-driven debug
  • Reusable CBB/IP components

Public feedback

Use community discussions for non-confidential feedback. Keep private source code and proprietary design documents out of public channels.