Example

Verilog FSM generator example

Use genRTL to describe a finite state machine in engineering terms, then generate reviewable Verilog/SystemVerilog with states, transitions, outputs, and verification checks.

Open generator Back to genRTL

Typical input

Describe reset behavior, input events, output timing, illegal states, and timing constraints. genRTL can translate that into an FSM plan before implementation.

Reset to IDLE with deterministic outputs
Handshake transitions for START, DATA, WAIT, and DONE
Assertions for illegal transitions and output validity

Typical output

The resulting RTL can include enumerated states, next-state logic, registered outputs, and assertions that help catch protocol or reset mistakes during simulation.

Verilog or SystemVerilog module skeleton
Combinational next-state and sequential state registers
Simulation checks for expected transitions