genRTL Docs
Public product docs for digital front-end / FPGA workflows

Public product docs

Covers user-facing workflows only, not internal orchestration or private implementation details.

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Concepts

The fastest way to use genRTL well is to understand the difference between planning, implementation, repair, reuse, and evidence-driven validation.

Schem, Agent, and Debug

Schem Mode is for planning. Agent Mode is for writing or changing code. Debug Mode is for evidence-backed repair. Keeping these jobs separate improves clarity and avoids jumping into code too early.

CBB-first thinking

CBB stands for reusable building blocks that are already mature enough to prefer reuse over regeneration. When a task matches a known component well, reuse can reduce risk, shorten review time, and improve predictability.

Assertion-aware validation

genRTL treats assertions as a practical accelerator for hardware verification. Assertions help catch protocol, handshake, reset, and sequencing mistakes earlier, and they give Debug Mode better signals than free-form guesswork alone.