Get Started
Installation
Installation is intentionally lightweight. The editor provides the interactive experience, while the SaaS backend handles generation and coordination.
Editor setup
Install the genRTL client in the supported editor environment, then sign in with your genRTL account. Once connected, the extension can route your requests to the backend and return structured outputs in the workspace.
Workspace preparation
A clean workspace makes the first run easier to review. Keep source files, simulation files, and notes separate. Start with a small design target before attempting a large multi-block subsystem.
- Create clear folders for rtl, tb, sim, and notes
- Keep specs or design notes in the workspace
- Include existing house rules or coding constraints when needed
Required: install a local EDA simulator
genRTL generates RTL source files and testbenches, but it does not include a built-in simulator. You must have at least one of the following EDA simulators installed and runnable on your local machine before you can compile or simulate the output.
- Questa Advanced Simulator (Siemens EDA) — supports full SystemVerilog and UVM; recommended for most flows
- Synopsys VCS — standard in ASIC tape-out environments; supports full SystemVerilog and Formal
No simulator = no simulation feedback
Without a local simulator you can still use genRTL to generate and review RTL source files, but Debug Mode cannot process compile errors or simulation logs.
Make sure the simulator is on your PATH
After installing the simulator, verify the binary is reachable from the terminal you use with Cursor. Run a quick version check before starting genRTL:
- Questa: vsim -version
- VCS: vcs -ID
Tip: use the simulator scripts genRTL generates
When genRTL produces a new design it also generates simulator-specific run scripts (filelist_rtl.f, run_questa.do, run_vcs.sh, etc.). You can use these scripts directly, or adapt them to your existing Makefile or CI flow.