genRTL Docs
Public product docs for digital front-end / FPGA workflows

Public product docs

Covers user-facing workflows only, not internal orchestration or private implementation details.

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Core Workflows

Debug Mode

Debug Mode is for fixing things after something has gone wrong. It works best when the input includes compile diagnostics, simulation failures, assertion results, or concise evidence extracted from the workspace.

Best input for Debug Mode

The more concrete the evidence, the better the repair loop. Error text, assertion failures, nearby code snippets, and a short explanation of the expected behavior usually produce better results than a vague request to make the design work.

Prefer minimal repair

Good repair output should be small, targeted, and easy to review. A fix that changes half the project is usually higher risk than a fix that adjusts the actual root cause.

What not to do

Do not use Debug Mode as a substitute for architecture planning. If the plan is wrong, go back to Schem Mode. Also avoid asking Debug Mode to blindly rewrite mature reusable components unless you have strong reason to do so.