Get Started
Quickstart
This page shows the shortest useful path: describe a block, review the plan, generate the implementation, then validate and iterate.
Recommended first run
Start with a small but real module such as a UART controller, APB slave, FIFO wrapper, or timing generator. Ask genRTL to begin with design planning rather than code, then confirm the block boundary, interfaces, and verification targets before asking for implementation.
- Create or open a workspace
- Describe the target block, interface, and constraints
- Run Schem Mode first
- Review module split, ports, reset behavior, and test intent
- Switch to Agent Mode for implementation
- Use Debug Mode only after you have evidence such as compile errors, assertions, or simulation logs
A good first prompt
A strong prompt includes the block purpose, interface, clock/reset behavior, throughput assumptions, corner cases, and what you expect in verification. For example: design an APB-controlled UART TX with configurable baud divider, clean reset behavior, and a smoke testbench.
Review before you accept output
Treat the first result as a candidate, not the final truth. Review naming, interface boundaries, reset semantics, state transitions, and storage choices. If the design should reuse an existing internal building block, prefer that path instead of accepting a fresh rewrite.
Do not skip review
Even when the generated code looks plausible, you should still review ports, timing assumptions, and verification intent before moving on.