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Public product docs for digital front-end / FPGA workflows

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Covers user-facing workflows only, not internal orchestration or private implementation details.

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Core Workflows

Schem Mode

Schem Mode is where you turn an informal idea into a clearer implementation plan. It should reduce ambiguity before code is written.

When to use it

Use Schem Mode when the requirements are incomplete, the interface is still moving, or the block should be split into multiple modules. It is especially useful before generating control-heavy logic, protocol engines, or reusable modules.

Expected output

A good Schem result usually defines module boundaries, main signals, state responsibilities, storage choices, reset behavior, and verification focus. The output should be specific enough to guide implementation but not so rigid that it hides design judgment.

Review checklist

Before moving to Agent Mode, confirm that the plan reflects the architecture you actually want.

  • Correct top-level interfaces and naming
  • Reasonable module split
  • Clear reset and clocking assumptions
  • Expected state-machine responsibilities
  • Verification targets that match the risk of the block