genRTL Docs
Public product docs for digital front-end / FPGA workflows

Public product docs

Covers user-facing workflows only, not internal orchestration or private implementation details.

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Verification & Debug

Assertion Workflow

Assertions help genRTL move from “something failed” to “this property failed under this condition.” That usually makes review and repair much faster.

When assertions help most

Assertions are especially useful around handshakes, state transitions, FIFO safety, reset behavior, register access, and protocol sequencing. They are often worth generating when new RTL or a new scaffold introduces behavioral risk.

What this page covers publicly

The docs explain when to use assertions, how to review the idea of an assertion-backed flow, and how to interpret results at a high level. Internal binding details, private orchestration checks, and implementation-specific automation remain product internals.

Practical loop

A practical assertion loop is simple: define the expected behavior, generate or refine the checks, run validation, inspect the failure, then apply a minimal repair. The key is to use assertions as concrete signals, not just as extra files in the repository.